To increase the integration of a semiconductor device, such as multi-gate transistors including a fin-type multi-channel active pattern (and/or silicon body) on a substrate and a gate on the multi-channel active pattern have been proposed.
Since a multi-gate transistor can utilize a three-dimensional channel, it can be scaled. Further, current control capability can be improved without increasing a gate length of the multi-gate transistor. A short channel effect (SCE) that the electrical potential of the channel region is effected by the drain voltage can be effectively reduced and/or suppressed in the multi-gate transistor.